A network processor is one example of what is more generally referred to herein as a link layer device, where the term “link layer” generally denotes a switching function layer, also referred to as the data link layer in the well-known Open Systems Interconnection (OSI) model. Network processors and other link layer devices are commonly used to implement processing associated with various packet-based and cell-based protocols, such as, for example, Internet protocol (IP) and asynchronous transfer mode (ATM).
Communication between a physical layer device and a network processor or other type of link layer device may be implemented in accordance with an interface standard, such as the POS-2 standard described in “POS-PHY Saturn Compatible Packet Over SONET Interface Specification for Physical Layer Devices,” Level 2, PMC-Sierra, Inc., 1998, which is incorporated by reference herein. Another example of a known interface standard is the SPI-3 interface standard described in Implementation Agreement OIF-SPI3-01.0, “System Packet Interface Level 3 (SPI-3): OC-48 System Interface for Physical and Link Layer Devices,” Optical Internetworking Forum, 2001, also incorporated by reference herein.
A given physical layer device may comprise a multiple-port device which communicates over multiple channels with the link layer device. Such communication channels, also commonly known as MPHYs, may be viewed as examples of what are more generally referred to herein as physical layer device ports. A given set of MPHYs that are coupled to a link layer device may comprise multiple ports associated with a single physical layer device, multiple ports each associated with one of a plurality of different physical layer devices, or combinations of such arrangements. As is well known, a link layer device may be advantageously configured to detect backpressure for a particular MPHY via polling of the corresponding MPHY address on its associated physical layer device. The detected backpressure is used by the link layer device to provide flow control and other traffic management functions, thereby improving link utilization.
The above-noted interface standards generally specify techniques for addressing an MPHY and for moving payload data over the interface. The addressing may use the same or separate pins from the payload. For the POS-2 standard, the MPHY address uses pins that are separate from the payload, and the maximum number of MPHYs that can be specified is 31. There are well-known extensions to the POS-2 standard that increase the maximum number of MPHYs in increments of 31 by using additional pins. For the 8-bit mode of the SPI-3 standard, the MPHY address uses eight payload pins and thus the maximum number of MPHYs that can be specified is 28=256.
U.S. patent application Ser. No. 11/466,858, filed Aug. 24, 2006 in the name of inventors A. P. Henry et al. and entitled “Port Addressing Method and Apparatus for Link Layer Interface,” which is incorporated by reference herein, discloses efficient techniques for supporting much larger numbers of MPHYs in a multiservice environment while maintaining compliance with one or more interface standards. These techniques avoid the need for additional address pins, and also overcome other MPHY addressing problems of conventional practice, such as excessive memory requirements and bandwidth reduction.
Another issue that can arise in utilizing standard interfaces such as POS-2 and SPI-3 relates to packet preemption. Such packet preemption is permitted in, for example, certain applications in which the physical layer device comprises a digital subscriber line (DSL) transceiver. As a more particular example, ITU-T Recommendation G.993.2, “Very High Speed Digital Subscriber Line 2,” February 2006, which is incorporated by reference herein, describes the standard requirements for a type of DSL referred to as VDSL-2. The VDSL-2 standard defines packet preemption as allowing for the transport of high-priority and low-priority packet flows through a single bearer channel. Typically, the transmission of a low-priority packet is paused, a high-priority packet is transmitted, and then the transmission of the low-priority packet is resumed. The VDSL-2 standard further states that preemption minimizes the packet insertion delay for the high-priority packets at the expense of a higher delay for the low-priority packets. Such preemption allows delay-critical traffic such as voice and video packets to have priority over other data packets such as web pages, email, etc.
In the VDSL-2 context, packet preemption is used in packet transfer mode, where packets are transferred to the VDSL-2 transceiver from a link layer device such as a network processor. The above-noted POS-2 or SPI-3 interfaces may be used to provide the interface between the VDSL-2 transceiver and the link layer device. Unfortunately, conventional implementations of the POS-2 or SPI-3 interfaces do not provide sufficient support for packet preemption. As a result, more complex signaling approaches are required, which can unduly increase the costs associated with a given implementation.
The above-cited U.S. patent application Ser. No. 11/536,191 provides techniques for configuring otherwise standard interfaces such as POS-2 or SPI-3 to facilitate the provision of multilevel packet preemption for DSL and other applications. Illustrative embodiments described therein provide multilevel packet preemption based on balancing of start and end indictors. By way of example, an arbitrary number n of levels of preemption may be provided, wherein n consecutive start indicators are received for n respective packets, and preemption of each of n−1 packets by packet n is confirmed by subsequent receipt of n consecutive end indicators. In one of the illustrative embodiments, the packets are directed to a common MPHY address, and the consecutive start indicators comprise multiple consecutive assertions of an xSOP signal for the same MPHY without intervening assertions of an xEOP signal. The multiple consecutive assertions of the xSOP signal for the same MPHY without intervening assertions of the xEOP signal are recognized as being indicative of appropriate preemptions if and only if followed by an equivalent number of consecutive assertions of the xEOP signal.
Despite the considerable advantages provided by the techniques disclosed in the above-cited U.S. patent application Ser. No. 11/536,191, a need remains for further improvements in packet preemption. For example, it would be desirable if a preemption technique could allow multiple high-priority packets to preempt a single low-priority packet.